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LHF08CTE
23
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to
accommodate multiple memory connections.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY# and Block Erase, Byte Write,
and Lock-Bit Configuration Polling
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, byte write
and lock-bit configuration completion. It transitions
low after block erase, byte write, or lock-bit
configuration commands and returns to V OH when
the WSM has finished executing the internal
algorithm.
RY/BY# is also V OH when the device is in block erase
suspend (with byte write inactive), byte write suspend
or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a 0.1μF ceramic capacitor
connected between its V CC and GND and between its
V PP and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7μF electrolytic capacitor should be placed at the
array’s power supply connection between V CC and
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 V PP Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V PP Power supply trace.
The V PP pin supplies the memory cell current for byte
writing and block erasing. Use similar trace widths
and layout considerations given to the V CC power
bus. Adequate V PP supply traces and decoupling will
decrease V PP voltage spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
Rev. 1.3
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